Parallel Testing of Parametric Faults in a Three-Dimensional Dynamic Random-Access Memory
نویسنده
چکیده
-Ihis paper presents a testable design of dynamic randomaccess memory (DRAM) architecture which allows one to access multiple cells in a word l i e simultaneously. The technique utilizes the two-dimensional (2D) organization of the DRAM and the resulting speedup of the conventional algorithms is considerable. This paper specifically investigates the failure mechanisms in the three-dimensional (3D) DRAM with trench-type capacitor. As opposed to the earlier approaches for testing parametric faults that employed sliding diagonal-type tests with O ( n 3 / 2 ) complexity, the algorithms discussed in this paper are different and have O ( m ) complexity, where p is the number of subarrays within the DRAM chip. These algorithms can be applied externally from the chip and also they can be easily generated for built-in self-test (BIST) applications.
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